A arithmetic processing unit (processor, central processing unit (CPU)) has a cache memory to avoid a long latency for accessing a main storage unit (main memory) provided outside. The cache memory stores data read out from the main memory when the processor executes a memory access instruction. Then, when executing the memory access instruction again for the same address, the processor reads out the data from the cache memory (that may be hereinafter called a “cache”) to avoid accessing the main memory.
When the instruction issuance unit of the processor issues a load instruction or a storage instruction, a memory access request is input to a cache. Then, the cache makes a cache determination as to whether the data of the access address has been retained or registered in the cache memory. When a cache hit has occurred, the cache returns the data response of data in the cache memory (returns the response with the data) to the instruction issuance unit. On the other hand, when determining that a cache miss has occurred, the cache issues a move-in request to a low-level cache closer to the main memory or a memory control circuit.
The move-in request is a request in which a certain-level cache requests a low-level cache closer to the main memory or the memory control unit to return the data of the access address, i.e., a type of the memory access request. The move-in request is issued by a cache in which a cache miss has occurred.
The move-in request is disclosed in International Publication Pamphlet No. WO2007/088591 and Japanese Laid-open Patent Publication No. 2001-51899.
Since it may take a long time from the issuance of a move-in request to a data response thereto, a move-in buffer for registering therein information indicating that the move-in request has been issued is provided, for example, between an L1 cache and an L2 cache (or between the L2 cache and an L3 cache). When issuing the move-in request, the L1 cache acquires the move-in buffer and registers, in the move-in buffer, the index information of the move-in request, i.e., the index information (index address) of a cache memory in which a cache miss has occurred and the way information of the cache in which response data is to be registered after a data response.
After the L2 cache issues an ejection request for ejecting old data having been registered in the L1 cache and the data is ejected from the L1 cache to the L2 cache, the L1 cache receives a data response from the L2 cache and stores new data in the data region of a corresponding move-in buffer. Then, the L1 cache registers the returned data in an L1 cache memory based on the index information and the way information that have been registered in the move-in buffer, and returns a data response to the instruction issuance unit (or an upper level cache more distant from the main memory). After receiving the data response, the move-in buffer that has registered the information of the move-in request is released. By registering a plurality of move-in request information in the move-in buffer, the L1 cache issues the next move-in request before receiving a data response for a preceding move-in request.